At present, thin film transistor liquid crystal display (TFT-LCD) devices, as a main flat-panel display device in the existing technologies, have become an important display platform of modern IT products and video products. LCD devices are widely used in all kinds of electronic products. During the manufacturing process of LCD devices, there is an important technology called Gate Driver On Array (GOA) technology. GOA technology aims to realize line-by-line scanning of a gate drive circuit by providing a line-scanning drive signal circuit of a gate drive circuit on an array substrate of a LCD panel. This gate drive circuit integrated on an array substrate by means of GOA technology is called a GOA gate drive circuit or a GOA circuit.
An existing GOA circuit usually comprises multiple stages of GOA units that are cascaded. A GOA unit in each stage drives a horizontal scanning line in a corresponding stage. A GOA unit mainly comprises a pull-up part, a pull-up control part, a transfer part, a key pull-down part, a pull-down holding part, and a bootstrap capacitor configured to increase an electrical potential.
The pull-up part is mainly configured to output a clock signal as a gate drive signal. The pull-up control part is configured to control the on-state time of the pull-up part and is generally connected with a transfer signal or a gate drive signal (for short, a gate signal) transmitted from a previous-stage GOA circuit. The key pull-down part is configured to pull down the gate drive signal to a low level, that is, to turn off the gate drive signal. The pull-down holding part is configured to hold an output signal of the gate drive signal and the gate drive signal (usually called Q point) of the pull-up part in an off state (i.e. in a negative level). Usually there are two pull-down holding parts working alternately. The bootstrap capacitor is responsible for a secondary pulling-up of Q point, which is conducive to an output of G(N) of the pull-up part.
FIG. 1 schematically shows a GOA circuit in the prior art. As shown in FIG. 1, an Nth-stage GOA unit is configured to charge an N-stage horizontal scanning line G(N) in an active area. The Nth-stage GOA unit comprises a pull-up control part 100, a pull-up part 200, a transfer part 300, a bootstrap capacitor 400, a key pull-down part 500, a first pull-down holding part 600, and a second pull-down holding part 700.
The pull-up control part 100 comprises a TFT T11. A gate of the TFT T11 is configured to input a transfer signal ST(N−1) of an (N−1)th-stage GOA unit, and a drain and a source thereof are respectively connected with a horizontal scanning line G(N−1) in an (N−1)th stage and a gate signal point Q(N). The pull-up part 200 comprises a TFT T21. A gate and a source of the TFT T21 are respectively connected with the gate signal point Q(N) and a horizontal scanning line G(N) in an Nth stage, and a drain thereof is configured to input a clock signal CK. The transfer part 300 comprises a TFT T22. A gate of the TFT T22 is connected with the gate signal point Q(N), and a drain and a source thereof are configured to respectively input the clock signal CK and output a transfer signal ST(N). The key pull-down part 500 comprises a TFT T31 and a TFT T41. A gate and a drain of the TFT T31 are respectively connected with a horizontal scanning line G(N+1) in an (N+1)th stage and the horizontal scanning line G(N) in the Nth stage, and a source thereof is configured to input a direct-current (DC) low voltage VSS. A gate and a drain of the TFT T41 are respectively connected with the horizontal scanning line G(N+1) in the (N+1)th stage and the gate signal point Q(N), and a source thereof is configured to input the direct-current low voltage VSS.
The pull-down holding part comprises two mirroring pull-down holding parts, a first pull-down holding part 600, and a second pull-down holding part 700.
During working, a first clock signal LC1 and a second clock signal LC2 both have a frequency lower than that of the clock signal CK inputted into the pull-up part 200 and a first circuit point K(N) and a second circuit point P(N) are configured to be at a high level alternately, so that the two pull-down holding parts work alternately. By way of this, TFTs of the two pull-down holding parts are protected from constant DC-stress and negative effects resulted therefrom can thus be alleviated.
Yet, the existing shift registers allows scanning only in a specific direction (e.g. drive gate lines G(1) to G(N) in turn by way of forward scanning) and are not able to support other drive modes. As the existing shift registers are provided with only one drive mode, LCD panels are restricted in use.